Vaseem Ahmed Qureshi
Faculty Associate
vaseem.qureshi@mahindrauniversity.edu.in
Vaseem Ahmed Qureshi is an accomplished academician with over 18 years of teaching and research experience. His research area includes Digital IC Design, Nano Computing and Quantum Dot Cellular Automata. He has published numerous research papers in reputed journals and conferences. He has actively contributed to curriculum development, outcome-based education processes, and has organized and delivered workshops and faculty development programs. His expertise spans advanced EDA tools and programming languages, making him a valuable contributor to both academia and research innovation.
Pursuing Ph.D.
- Pursuing Ph.D. in VLSI Design at the National Institute of Technology, Patna, Bihar, India
M.Tech
- Master of Technology in VLSI System Design from VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, Telangana, India in 2008
B.Tech
- Bachelor of Technology in Electronics & Communication Engineering from Arkay College of Engineering and Technology, Nizamabad, Telangana, India in 2005
Experience
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Vaseem Ahmed Qureshi is currently working as a faculty associate at Mahindra University (2025).
- Worked as Associate Professor in the department of Electronics and Communication Engineering at CMR Engineering College from 2011 to 2025.
- Worked as Assistant Professor in the department of Electronics and Communication Engineering at MNR College of Engineering and Technology from 2008 to 2011.
- Worked as Assistant Professor in the department of Electronics and Communication Engineering at Arkay College of Engineering and Technology from 2005 to 2006.
Publications
2024
- “Efficient Adders for Nano Computing: An Approach Using QCA”, Physica Scripta, IOP Publishing Ltd., Volume 100, 015019, December 2024.
- “Designing and Developing a Dependable and High-Throughput Model with Enhanced DNN Using ABC Algorithm”, 1st International Conference on Sustainable Computing and Integrated Communication in Changing Landscape of AI (ICSCAI), Greater Noida, India, July 2024, pp 1-5
2023
- “An Optimized FIR Filter Design for Phase Based Processing Using Verilog HDL”, AIP Conference Proceedings, ISBN 2477, 030022, July 2023.
2022
- “Design and implementation of error detection and correction system for semiconductor memory applications”, IET Conference Proceedings, ISSN 2732-4494, April 2022.
2021
- “Implementation of Quantum Dot Cellular Automata Based Efficient N Bit BCD Adders Using Verilog”, IOP Journal of Physics Conference Series, ISBN 1964062092, August 2021.
2020
- “Design of Parallel Prefix Adder and Subtractor using Majority Logic Formulations”, IOP Conference Series: Materials Science and Engineering, ISBN 1757-899X, November 2020.
2019
- “A 128 Bit Tunable True Random Number Generator with Digital Clock Manager”, Recent Trends and Advances in Artificial Intelligence and Internet of Things, International Systems Reference Library, Volume 172 Springer ISBN 978-3-030-32644-9, November 2019.
2014
- “Design and Development of FPGA Based Automated Test System”, National Conference on Signal Processing, Communications & System Design (SPCOM-SD) held on 3rd and 4th January 2014 at Malla Reddy Engineering College for Women, Hyderabad.
2011
- “Hybrid System for Observing People Inside Buildings Using Zigbee and RFID”, National Conference on Emerging Trends & Techniques in Electronics & Communication Engineering, held on 17th and 18th March 2011 at Lords Institute of Engineering & Technology, Hyderabad.
- Digital IC Design
- Nano Computing
- Quantum dot Cellular Automata
