P B Natarajan

P B Natarajan is an electronics and VLSI graduate with a strong blend of academic, industry, and research experience. He holds a B.Tech. in Electronics and Communication Engineering from CEB, Bhubaneswar, an M.Tech. in VLSI Chip Design from JNTUH, Hyderabad, and he is currently pursuing his Ph.D. in Hardware Security in VLSI Chips at IIT Hyderabad.

His career also includes 2 years of industry experience in the embedded domain at Bharat Electronics Limited (BEL), Delhi, along with over 10 years of teaching experience at engineering colleges, where he has taught subjects such as Digital Electronics, Analog Electronics, Microprocessors, Verilog HDL, and VLSI Chip Design (RTL to GDSII).

He also has 5 years of dedicated research experience at IIT Hyderabad, focusing on hardware security challenges in VLSI chip design. In addition, he has actively participated in numerous national and international conferences, workshops, and seminars, which have helped him stay updated with the latest advancements in VLSI, embedded systems, and hardware security, while also contributing to his research and professional growth.

• Pursuing Ph.D. (Hardware Security in VLSI Chips). IIT Hyderabad, Sangareddy, Telangana, India.

• M.Tech. (VLSI chip Design) JNTUH, Hyderabad, India.

• B.Tech. (ECE) CEB, Bhubaneswar, Odisha, India.

Publications

• PB Natarajan, SK Ghosh, R Karthik. Low-power, high-performance carry-select adder
• VSR Subrahmanyam, PB Natarajan, V Kavya. Area Efficient Approximate Constant-or Adder.
• SVS Prasad, PB Natarajan, LB Shankar. Broadening 3-bit burst error-correction codes with quadruple adjacent error correction.
• PB Natarajan, SK Ghosh. Design and implementation of smart car parking system using lab view
• SK Ghosh, PB Natarajan, SB Prusty. Intelligent Smart Home Automation System based on LabVIEW

• Having 2 years Industry Experience in embedded Domain (B.E.L Delhi).
• Having 10 years Teaching Experience in different Engineering Colleges.
  Subjects Handled: Digital Electronics, Analog Electronics, Microprocessors, Verilog HDL, VLSI Chip Design complete RTL to GDSII.

• Having 5 years Research Experience at IIT Hyderabad.

• His research primarily focuses on advancing VLSI Chip Design with a strong emphasis on performance optimization and security. His work on integrating AI/ML algorithms into VLSI architectures enables efficient optimization in terms of area, power, and delay, ultimately achieving next-generation intelligent hardware solutions.
• A significant part of his work also addresses hardware security in VLSI chips, developing techniques to protect circuits against reverse engineering (RE), side-channel attacks, and other emerging threats. His research also spans across the Physical Design flow, including Static Timing Analysis (STA), sign-off checks, physical verification, and complete RTL-to-GDSII implementation.
• In addition, he also actively explores methodologies for RTL design and verification, ensuring functional correctness and design robustness at the early stages of chip development. His broader goal is to bridge the gap between algorithmic innovations and practical silicon implementations by leveraging AI/ML for design automation, optimization, and security enhancement in VLSI systems.